Electrostatic discharge (ESD) is sudden and momentary electric current that flows between two objects at different electrical potentials caused by direct contact or induced by an electrostatic field. ESD is a serious issue in solid state electronics, such as integrated circuits. For example, integrated circuits are made from semiconductor materials such as silicon and insulating materials such as silicon dioxide and either of these materials can suffer permanent damage when subjected to high voltages. As a result, there are now a number of structures that help protect against ESD in integrated circuits.
ESD protection in past silicon on insulator (SOI) technologies relied on the use of poly-bound diodes. However, in advanced SOI technologies, the use of a standard “double diode” ESD protection structure is no longer sufficient for a number of reasons: (1) input/output operating voltages of devices are larger, (2) the devices fail at lower voltages, and (3) higher frequency input/outputs of the devices require lower capacitance solutions.
Field-effect transistors (FETs) with silicide blocking on the source and drain provide an alternative solution that meets the requirements of some input/output designs of these devices. In certain SOI processes, nitride used for the silicide blocking is shared with a spacer nitride. In particular, only extension and halo implants occur in the area blocked by silicide formation, which is an advantage for ESD protection, since this design increases the sheet resistance in the silicide blocked region. Specifically, a smaller silicide blocking length can be used to achieve the desired sheet resistance.
FETs created in this process with a single silicide blocking mask shape that extends from the drain to the source provides good ESD characteristics. However, this configuration is disadvantageous because (1) the configuration causes a significant increase in capacitance at the interface between the extensions and the P-well, which is undesirable in high speed input/output designs, and (2) the silicide blocking prohibits the ability to silicide the gate for enhanced electrical contact.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.